Field of the Technology
The present disclosure relates to high density memory devices, and to the operation of devices storing multiple bits per cell.
Description of Related Art
NAND flash memory is widely adopted as a storage medium for mobile devices, solid-state disks in laptops and servers and for other data processing systems. In order to improve the data density on NAND flash memory chips, vendors have been using multilevel-cell (MLC) technology to store two or more bits of information in each cell. However, MLC chips usually suffer from a longer latency in read and program operations, shorter retention time, and more reliability concerns due to smaller gaps among the threshold voltages of different bit values, compared to single-level-cell (SLC) chips in which each cell stores one bit of information.
In MLC flash memory, programming the high and low pages of the same word line can be divided into two stages, because it is not guaranteed that data of both pages are ready in the page buffer for programming. See, Chang, et al., “A reliability enhancement design under the flash translation layer for mlc-based flash-memory storage systems,” ACM Trans. Embed. Comput. Syst. 13(1):10:1-10:28. September 2013. For example, all the cells of the same word line are initially at the state with the lowest (sensing) threshold voltage. At the first stage, the high page data are first programmed to the word line. The flash cells storing bit 1's (of the high page) remain in the same state, but the cells storing bit 0's are programmed forward to (logical) state “0” that has higher threshold voltage. Such a cell distribution is similar to that after the programming of an SLC page. Thus, the programming speed of a high page is very close to that of an SLC page.
At the second stage, the low page data are programmed to the word line to have cells distributed to four different states, so that each cell can represent two bits of data, one from the high page and the other from the low page. The cells in state “1” are programmed forward to state “10” if they store bit 0's of the low page; otherwise, they are programmed to state “11”. Similar operations are also applied to the cells in state “0”.
The programming algorithm for the second stage requires finer control over the final distribution in threshold voltages. So, programming a low page will take a much longer time than programming a high page. Such a design leads to time-consuming delay on programming low pages, and seriously harms the overall programming speed and access performance in MLC flash memory. In addition, such a design will also result in a larger number of error bits or a higher bit error rate, because the voltage range required for the multiple levels (below Vpass) is partitioned into more states. Note that Vpass is the voltage that can turn on flash cells in any data storage state.
Some MLC programming methods were proposed for the situation that data of both high and low pages are ready in the page buffer at the same time, such as described in U.S. patent application Ser. No. 14/153,934, entitled PROGRAMMING MULTIBIT MEMORY CELLS; by Hsieh et al., filed on 13 Jan. 2014 (now US Pat. Pub. No. 2014/0198570). These can improve performance at the cost of greater constraints on operation of the devices.
It is desirable therefore, to provide improved operating methods for MLC memory, to improve throughput, reduce average latency and improve reliability.